Integrated circuits (ICs) are being deployed in large volumes in many different environments. In a typical scenario, a designer generates a design using various software design tools. The design is then used to fabricate potentially a large number of ICs. It is generally desirable that the ICs operate for a long time, at least under their intended operating conditions.
Accordingly, it is typically necessary to analyze the design to determine whether the corresponding ICs are likely to fail over a period of time. Failure rate is a parameter which is used to measure the probability of failure of an integrated circuit over a long period of time. According to certain methodologies for testing, a great number of devices are tested for a relatively short period of time and the number of devices failing is termed as the failure rate. If the failure rate is determined to be unacceptably high, a designer may have an opportunity to redesign the IC to achieve an acceptable failure rate, assuming the same manufacturing process.
A well-known reason for failure of an integrated circuit is the wearout (or degradation in general) of gate oxide contained in transistors, which form the integrated circuits. As is also well-known, gate oxide is commonly used as an insulator in the gate of components such as MOSFETs (metal oxide semi-conductor field effect transistors) and the insulator degrades typically under continuous biases and signal overshoots (in positive and negative directions) at the gate terminal.
An overshoot generally refers to the voltage level of a signal which is in excess of the voltage level defining a corresponding logical level. For example, a logical level of 1 may be represented by 1.5 V and voltage levels exceeding 1.5 V are referred to as overshoots. Similarly, assuming 0 voltage level represents a logical value of 0, excessive negative voltage may also be referred to as undershoot or overshoot (in the negative direction).
One challenge in analyzing such integrated circuits (for determining the failure rate) is that typical integrated circuits contain a large number of transistors and analyzing the possible voltage range of the input signals at each transistor will consume a long period of time. The resulting long analysis times are unacceptable, at least in situations where it is desirable to keep the design cycle time short. To provide for an accurate measurement of the failure rate and lifetime projection (or maximum Vcc) for microprocessors and other semiconductor products, stress voltages are applied to the products. The efficiency and accuracy of the calculation for determination of the failure rate and lifetime projection are dependent on the range of applied stress voltages. A broad range of stress voltages that are close to the actual operational voltage of the circuit provides high accuracy. On the other hand, the use of voltages close to the operating voltage will require a long period of time to determine the failure rate and lifetime projection or maximum Vcc calculation. The relatively short product life cycle of high performance microprocessors, however, demands an efficient qualification with a reasonable time dependent dielectric breakdown (TDDB) test period. Hence, long-term stresses of the semiconductor products at low voltages are not practically favored.